FIG. 8 is a diagram illustrating circuit construction of a prior art semiconductor memory device. In the figure, reference numeral 1 designates an address decoder. Reference numerals A0 to A31 designate address lines that are output lines of the address decoder 1 for selecting memory elements. Reference numeral 2 designates data input D.sub.IN, numeral 3 designates data output D.sub.OUT, numeral 4 designates a data line, and numeral 5 designates an inverted data line. Each block 8, comprising n channel transistors 6 and 7 for selecting a memory element indicated by an address line, an inverter 11 comprising a p channel transistor 21 and an n channel transistor 31, and an inverter 12 comprising a p channel transistor 22 and an n channel transistor 32, is connected to one of address lines A0 to A31, respectively. Reference numeral 9 designates a writing enable signal for indicating writing in or reading out of data to or from memory elements. Reference numerals 10 and 20 designate drivers for writing in, which drive a data line 4 and an inverted data line 5, respectively. Reference numeral 30(C) designates a signal for initializing all memory elements, that is, a signal for writing data "0" in all memory elements.
FIGS. 9(a) and 9(b) are diagrams illustrating circuit constructions of the driver 10 for writing in data into a data line and the driver 20 for writing in data into an inverted data line, respectively. In FIG. 9(a), reference numeral 10a designates an inverter, numeral 10b designates a two-input NAND gate, numeral 10c designates a two-input NOR gate, numeral 10p designates a p channel transistor, and numeral 10n designates an n channel transistor. In FIG. 9(b), reference numerals 20a and 20d designate inverters, numeral 20b designates a two-input NAND gate, numeral 20c designates a two-input NOR gate, numeral 20p designates a p channel transistor, and numeral 20n designates an n channel transistor.
A description is given of the operation during writing in of the prior art semiconductor memory device.
During writing in, since the signal 9(WE) is "L", data input D.sub.IN and data input obtained from the data input D.sub.IN and inverted by the inverter 20d are applied to a data line 4 and an inverted data line 5 by writing drivers 10 and 20, respectively. Then, one of address lines A0 to A31, for example A0, is set "H" by an address decoder 1, and thereby the data D.sub.IN is written in into a selected memory element. At this time, a signal 30(C) is "L". Here, when data D.sub.IN is "L", "0" is written in memory elements while when the data D.sub.IN is "H", "1" is written in.
The operation at the initialization of memory elements is described. When a signal 30(C) is set "H", all address lines A0 to A31 are set "H", and the data input D.sub.IN is set "L", data "0" can be written in all memory elements. Then, an n channel transistor 10n of the writing driver 10 drives inputs of inverters 11, which are included in all thirty-two memory elements selected by the address lines A0 to A31, to "L" via a data line 4. A p channel transistor 20p of a writing driver 20 drives inputs of inverters 12, which are included in all thirty-two memory elements selected by the address lines A0 to A31, to "H" via an inverted data line 5.
When all memory elements are in states having data opposite to the initializing data, for example, when data "0" is to be input to all memory elements in state of data "1", the n channel transistor 10n of the driver 10 is required to reduce input voltages of inverters 11 of all memory elements to a value lower than the transition voltages of the inverters 11, overcoming drain voltages of the p channel transistors 22 (a parallel connection of thirty-two elements), one end of each of which is connected to power supply voltages.
Similarly, in all memory elements, the p channel transistor 20p of the driver 20 is required to increase input voltages of the inverters 12 to a value higher than the transition voltage of the inverters 12, overcoming drain voltages of the n channel transistors 31 (a parallel connection of thirty-two elements), one end of each of which is grounded.
Since the prior art semiconductor memory device is constructed as described above, when all memory elements are initialized, if a writing driver has a small driving ability, all memory elements cannot be initialized at the same time, i.e., writing in of the same data into all memory elements cannot be performed at the same time. Therefore, the size of the transistor of the writing driver must be increased in accordance with a total word line number, i.e., address line number, in order that writing in of the same data into all memory elements can be performed at the same time.